Reduced size semiconductor package with stacked dies

ABSTRACT

A semiconductor package comprising a plurality of leads. Each of the leads defines opposed first and second surfaces, and a third surface which is also disposed in opposed relation to the second surface. The first surface is oriented between the second and third surfaces. The semiconductor package further comprises first and second semiconductor dies which each define opposed first and second surfaces. Disposed on the first surface of the first semiconductor die are a plurality of bond pads, with bond pads also being disposed on the second surface of the semiconductor die. The first surface of the first semiconductor die is attached to the second surface of each of the leads, with the first surface of the second semiconductor die being attached to the second surface of the first semiconductor die. A plurality of conductive connectors or wires electrically connect the bond pads of the first and second semiconductor dies to respective ones of the leads. An encapsulating portion is applied to and at least partially encapsulates the leads, the first and second semiconductor dies, and the conductive connectors.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean Patent Application No.2001-02163 entitled SEMICONDUCTOR PACKAGE filed Jan. 15, 2001.

STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT

(Not Applicable)

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor packages, andmore particularly to a semiconductor package which includes a stackedpair of semiconductor dies, one of which is electrically connected tothe leads of the semiconductor package in a manner facilitating areduction in the size of the semiconductor package.

2. Description of the Related Art

As is well known in the electrical arts, recent advances insemiconductor package technology have led to the development ofpackaging techniques which provide for the continuing miniaturization ofthe semiconductor package. These advancements have also led to thedevelopment of a wide variety of new and differing types ofsemiconductor packages. Consistently in high demand are thosesemiconductor packages which have a high capacity and are capable ofperforming various functions. However, those currently knownsemiconductor packages including only a single semiconductor die arelimited in their ability to perform multi-functions. To address thislimitation, there has been developed in the prior art varioussemiconductor packages in which semiconductor dies or the semiconductorpackages themselves are stacked on each other. However, thesesemiconductor packages have structural limits attributable to thestacking of the dies or packages therein, and are often of a size whichdecreases or diminishes their utility in certain applications. Thepresent invention is specifically adapted to address this deficiency, aswill be discussed in more detail below.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided asemiconductor package which comprises a plurality of leads. Each of theleads defines opposed first and second surfaces, and a third surfacewhich is also disposed in opposed relation to the second surface. Thefirst surface is oriented between the second and third surfaces. Alsoincluded in the semiconductor package are first and second semiconductordies which each define opposed first and second surfaces. A plurality ofbond pads are disposed on the first surface of the first semiconductordie, with bond pads also being disposed on the second surface of thesecond semiconductor die. The first surface of the first semiconductordie is attached to the second surface of each of the leads, with thefirst surface of the second semiconductor die being attached to thesecond surface of the first semiconductor die.

In the semiconductor package, a plurality of conductive wires are usedto electrically connect the bond pads of the first semiconductor die torespective ones of the first surfaces of the leads. Conductive wires arealso used to electrically connect the bond pads of the secondsemiconductor die to respective ones of the second surfaces of theleads. An encapsulating portion is applied to the leads, the first andsecond semiconductor dies, and the conductive wires, with the thirdsurface of each of the leads being exposed within the encapsulatingportion.

In the semiconductor package of the present invention, the firstsemiconductor die and the leads are oriented relative to each other suchthat each of the bond pads of the first semiconductor die is locatedbetween a respective pair of the leads. As such, the bond pads of thefirst semiconductor die do not contact the second surface of any one ofthe leads. The conductive wires electrically connecting the bond pads ofthe first semiconductor die to the leads are thus oriented inwardlyrelative to the peripheral edge of the first semiconductor die. Thisrelative orientation facilitates a reduction in the size of thesemiconductor package.

The present invention is best understood by reference to the followingdetailed description when read in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

These, as well as other features of the present invention, will becomemore apparent upon reference to the drawings wherein:

FIG. 1 is a cross-sectional view of a semiconductor package constructedin accordance with the present invention;

FIG. 1A is a bottom plan view of the semiconductor package shown in FIG.1, excluding the encapsulating portion thereof;

FIG. 1B is a top plan view of the semiconductor package shown in FIG. 1,excluding the encapsulating portion thereof; and

FIGS. 2A through 2E are cross-sectional views illustrating a sequence ofsteps which may be employed for manufacturing the semiconductor packageof the present invention.

Common reference numerals are used throughout the drawings and detaileddescription to indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings wherein the showings are for purposes ofillustrating a preferred embodiment of the present invention only, andnot for purposes of limiting the same, FIG. 1 provides a cross-sectionalview of a semiconductor package 100 constructed in accordance with thepresent invention. The semiconductor package 100 comprises a pluralityof identically configured leads 130. Each of the leads 130 defines agenerally planar first (lower) surface 131 a and a generally planarsecond (upper) surface 131 b which is disposed in opposed relation tothe first surface 131 a. Each lead 130 further defines a generallyplanar third (lower) surface 131 c which is also disposed in opposedrelation to the second surface 131 b and is laterally offset outwardlyrelative to the first surface 131 a. More particularly, the thicknessbetween the second and third surfaces 131 b, 131 c exceeds the thicknessbetween the first and second surfaces 131 a, 131 b. The first surfaces131 a of the leads 130 are each preferably formed by a conventional halfetching technique using chemical solutions.

In addition to the leads 130, the semiconductor package 100 includes adie paddle 135 which is of a predetermined thickness. The preferredthickness of the die paddle 135 is preferably the same as the thicknessbetween the second and third surfaces 131 b, 131 c of each of the leads130. The leads 130 and die paddle 135 are oriented relative to eachother such that the leads 130 are arranged about the periphery of thedie paddle 135 in the manner best shown in FIG. 1A. The die paddle 135has a generally square configuration, with the leads 130 beingsegregated into four sets of four, and each set extending along arespective one of the four peripheral edge segments defined by the diepaddle 135. As seen in FIGS. 1 and 1A, the innermost end of each lead130 is disposed in spaced relation to the corresponding peripheral edgesegment of the die paddle 135. Those of ordinary skill in the art willrecognize that differing numbers of leads 130 in differing arrangementsmay be included in the semiconductor package 100, with the size, shapeand arrangement of the leads 130 and die paddle 135 as shown in FIGS. 1,1A and 1B being for exemplary purposes only.

The semiconductor package 100 of the present invention further comprisesa first semiconductor die 110 which defines a first surface 111 a and asecond surface 111 b which is disposed in opposed relation to the firstsurface 111 a. The first semiconductor die 110 further includes aplurality of bond pads 113 which are disposed on the first surface 111 athereof. In the semiconductor package 100, portions of the first surface111 a of the first semiconductor die 110 are bonded to the secondsurface 131 b of each lead 130 and to the top surface of the die paddle135 through the use of a layer of a die attach material 160. The dieattach material 160 may be any one of a non-conductive epoxy, anon-conductive polyimide, a non-conductive double-faced adhesive tape orits equivalent, with the present invention not being limited by anyparticular die attach material 160.

In addition to the first semiconductor die 110, the semiconductorpackage 100 includes a second semiconductor die 120. The secondsemiconductor die 120 defines a first surface 121 a and a second surface121 b which is disposed in opposed relation to the first surface 121 a.Disposed on the second surface 121 b are a plurality of bond pads 123.The first surface 121 a of the second semiconductor die 120 is bonded tothe second surface 111 b of the first semiconductor die 110 by anotherlayer of the die attach material 160.

As seen in FIG. 1A, the first semiconductor die 110 and leads 130 arearranged relative to each other such that the bond pads 113 of the firstsemiconductor die 110 are each oriented between a respective pair of theleads 130 when the first surface 111 a of the first semiconductor die110 is bonded to the second surfaces 131 b of the leads 130. In thisregard, it is important in the semiconductor package 100 that none ofthe bond pads 113 contact any of the second surfaces 131 b of the leads130 when the first surface 111 a of the semiconductor die 110 is bondedto the second surfaces 131 b of the leads 130. In the semiconductorpackage 100, each bond pad 113 of the first semiconductor die 120 iselectrically connected to the first surface 131 a of a respective one ofthe leads 130 by a first conductive connector 151 such as a conductivewire. Similarly, as seen in FIGS. 1 and 1B, each bond pad 123 of thesecond semiconductor die 120 is electrically connected to the secondsurface 131 b of a respective one of the leads 130 by a secondconductive connector 153 such as a conductive wire. The conductiveconnectors 151, 153 may each be any one of a gold wire, an aluminumwire, or its equivalent, with the present invention not being limited byany particular material for the conductive connectors 151, 153.

As indicated above, the bond pads 113 of the first semiconductor die 110are each located between a respective pair of leads 130. Thus, theelectrical connection between the bond pads 113 and the first surfaces131 a of the leads 130 through the use of the conductive connectors 151can be accomplished in a manner wherein the conductive connectors 151are each located inwardly relative to the peripheral edge of the firstsemiconductor die 110. As seen in FIG. 1, the peripheral edge of thefirst semiconductor die 110 extends to approximately that portion of thesecond surface 131 b of each lead 130 which is disposed in opposedrelation to the third surface 131 c.

In the semiconductor package 100, the first and second semiconductordies 110, 120, the leads 130, and the conductive connectors 151, 153 areeach encapsulated by an encapsulant in order to protect the same fromthe external environment. The hardening of the encapsulant defines anencapsulating portion 180 of the semiconductor package 100. Theencapsulating portion 180 is formed such that the third surface 131 c ofeach of the leads 130 and the bottom surface of the die paddle 135 areexposed within the encapsulating portion 180, and in particular thebottom surface defined thereby. Also exposed in the side surfaces of theencapsulating portion 180 is the outermost end of each of the leads 130.The exposed third surfaces 131 c of the leads 130 may be electricallyconnected to an external device (e.g., a motherboard). Additionally, theexposed third surfaces 131 c of the leads 130 and bottom surface of thedie paddle 135 within the encapsulating portion 180 function as heatsinks which allow for the emission of heat generated by the first andsecond semiconductor dies 110, 120.

It is contemplated that the first and second semiconductor dies 110, 120will have identical functions since the semiconductor dies 110, 120 areelectrically connected to common leads 130. However, it is alsocontemplated that the first and second semiconductor dies 110, 120 mayhave different functions. In this case, the first semiconductor die 110would be electrically connected to the first surfaces 131 a of certainones of the leads 130, with the second semiconductor die 120 beingelectrically connected to the second surfaces 131 b of certain ones ofthe leads 130 which are not electrically connected to the firstsemiconductor die 110. As such, the first and second semiconductor dies110, 120 would not be electrically connected to any common lead 130. Theorientation of the conductive connectors 151 inwardly of the peripheraledges of the stacked semiconductor dies 110, 120 allows for a reductionin the size of the semiconductor package 100.

Referring now to FIGS. 2A through 2E, the manufacturing method for thesemiconductor package 100 of the present invention preferably comprisesthe initial step of providing the leads 130 and die paddle 135 orientedrelative to each other in the above-described manner. Thereafter, thefirst surface 111 a of the first semiconductor die 110 is bonded to thesecond surface 131 b of each of the leads 130 and to the top surface ofthe die paddle 135 through the use of the die attach material 160 in theabove-described manner (FIG. 2A). As explained above, the firstsemiconductor die 110 and the leads 130 are oriented relative to eachother such that the bond pads 113 of the first semiconductor die 110 arenot in direct contact with any of the second surfaces 131 b of the leads130, but rather are each oriented between a respective pair of the leads130.

Subsequent to the attachment of the first semiconductor die 110 to theleads 130 and die paddle 135, the bond pads 113 of the firstsemiconductor die 110 are electrically connected to respective ones ofthe first surfaces 131 a of the leads 130 through the use of the firstconductive connectors 151 (FIG. 2B). Thereafter, the first surface 121 aof the second semiconductor die 120 is bonded to the second surface 111b of the first semiconductor die 110 by another layer of the die attachmaterial 160 (FIG. 2C).

Subsequent to the attachment of the second semiconductor die 120 to thefirst semiconductor die 110, the bond pads 123 of the secondsemiconductor die 120 are electrically connected to respective ones ofthe second surfaces 131 b of the leads 130 through the use of the secondconductive connectors 153 in the above-described manner (FIG. 2D).Thereafter, the encapsulant is applied to the first and secondsemiconductor dies 110, 120, the leads 130 and the first and secondconductive connectors 151, 153 to encapsulate the same and form theencapsulating portion 180 (FIG. 2E). As indicated above, theencapsulating portion 180 protects the first and second semiconductordies 110, 120, the leads 130, and the first and second conductiveconnectors 151, 153 from the external environment.

It is contemplated that the second semiconductor die 120 may be bondedto the first semiconductor die 110 via a layer of the die attachmaterial 160, with the first semiconductor die 110 thereafter beingbonded to the leads 130 in the above-described manner. It is furthercontemplated that the bonding order of the first and second conductiveconnectors 151, 153 used to facilitate the electrical connection of thefirst and second semiconductor dies 110, 120, respectively, to the leads130 can be changed or reversed from that described above if warranted bythe circumstance.

This disclosure provides exemplary embodiments of the present invention.The scope of the present invention is not limited by these exemplaryembodiments. Numerous variations, whether explicitly provided for by thespecification or implied by the specification, such as variations instructure, dimension, type of material or manufacturing process may beimplemented by one of skill in the art in view of this disclosure.

1-18. (canceled)
 19. A semiconductor package comprising: a plurality ofleads, each of the leads defining: a first surface; a second surfacedisposed in opposed relation to the first surface; and a third surfacedisposed in opposed relation to the second surface, the first surfacebeing oriented between the second and third surfaces; at least onesemiconductor die defining opposed first and second surfaces andincluding a plurality of bond pads disposed on the first surfacethereof, portions of the first surface of the semiconductor die beingdirectly attached to the second surface of each of the leads such thatat least some of the bond pads of the semiconductor die are locatedbetween and laterally adjacent to a respective pair of the leads so thatthe bond pads of the semiconductor die do not contact the second surfaceof any one of the leads; a plurality of conductive connectorselectrically connecting the bond pads of the semiconductor die to atleast some of the leads; and an encapsulating portion applied to and atleast partially encapsulating the leads, the semiconductor die, and theconductive connectors.
 20. The semiconductor package of claim 19 whereinthe conductive connectors comprise conductive wires.
 21. Thesemiconductor package of claim 19 wherein: the conductive connectorscomprise conductive wires; and at least some of the bond pads of thesemiconductor die are electrically connected to respective ones of thefirst surfaces of the leads by the conductive wires.
 22. Thesemiconductor package of claim 19 further comprising: a die paddledefining opposed top and bottom surfaces, the leads being disposed aboutthe die paddle; the first surface of the semiconductor die further beingattached to the top surface of the die paddle.
 23. The semiconductorpackage of claim 22 wherein the first surface of the semiconductor dieis attached to the second surface of each of the leads and to the topsurface of the die paddle by a first bonding means.
 24. Thesemiconductor package of claim 22 wherein: the die paddle is formed tohave a die paddle thickness; each of the leads is formed to have a leadthickness between the second and third surfaces thereof; and the diepaddle thickness is substantially equal to the lead thickness.
 25. Thesemiconductor package of claim 22 wherein the encapsulating portion isapplied to the die paddle such that the bottom surface of the die paddleis exposed in the encapsulating portion.
 26. The semiconductor packageof claim 25 wherein the encapsulating portion is applied to the leadssuch that the third surface of each of the leads is exposed in theencapsulating portion.
 27. The semiconductor package of claim 19 whereinthe encapsulating portion is applied to the leads such that the thirdsurface of each of the leads is exposed in the encapsulating portion.28. The semiconductor package of claim 19 wherein: the semiconductor diedefines a peripheral edge; and at least some of the conductiveconnectors electrically connecting the bond pads of the semiconductordie to the leads are oriented inwardly relative to the peripheral edgeof the semiconductor die.
 29. A semiconductor package comprising: aplurality of leads; at least one semiconductor die including a pluralityof bond pads disposed thereon, the semiconductor die being directlyattached to each of the leads such that at least some of the bond padsof the semiconductor die are located between and laterally adjacent to arespective pair of the leads so that the bond pads of the semiconductordie do not contact any of the leads; means for electrically connectingat least some of the bond pads of the semiconductor die to at least someof the leads; and an encapsulating portion applied to and at leastpartially encapsulating the leads, the semiconductor die, and theelectrical connection means.
 30. The semiconductor package of claim 29wherein the electrical connection means comprises conductive wires. 31.The semiconductor package of claim 30 wherein: each of the leads definesopposed first and second surfaces and a third surface which is opposedto the second surface, the first surface being oriented between thesecond and third surfaces; at least some of the bond pads of thesemiconductor die are electrically connected to respective ones of thefirst surfaces of the leads by the conductive wires.
 32. Thesemiconductor package of claim 31 wherein the encapsulating portion isapplied to the leads such that the third surface of each of the leads isexposed in the encapsulating portion.
 33. The semiconductor package ofclaim 29 further comprising: a die paddle, the leads being disposedabout the die paddle; the first semiconductor die being attached to thedie paddle.
 34. The semiconductor package of claim 33 wherein: the diepaddle defines opposed top and bottom surfaces, with the semiconductordie being attached to the top surface of the die paddle; and theencapsulating portion is applied to the die paddle such that the bottomsurface of the die paddle is exposed in the encapsulating portion.